Market requirements, environmental needs, business costs, and limited battery life dictate that computing devices use as little energy as possible while still providing robust computing services. The energy consumed by a computing device can be more efficiently managed by providing enough computational power for each service as needed instead of providing maximum computational power at all times. Computing devices, such as laptop, desktop, and mainframe computers, set-top boxes, entertainment and gaming systems, personal digital assistants (PDAs), cellular telephones, etc., provide services by causing program instructions to be executed by electronic circuitry. The electronic circuitry that executes computer program instructions in a computing device is often contained in a single integrated circuit referred to as a “core.” A core may be contained in a single physical package often referred to as a “central processing unit” (CPU). Those skilled in the art and others will recognize that multiple interacting cores may be contained in a CPU and that computers may have more than one CPU available to execute instructions.
Those skilled in the art and others will recognize that the CPU serves as the computational center of the computer by supporting the execution of program instructions. In this regard, the CPU follows a fetch and execute cycle in which instructions implemented by a program are sequentially “fetched” from an input/output (“I/O”) device via a bus. Then, to execute a fetched instruction, a sequence of control signals is transmitted to the relevant units of the CPU to perform the actions as directed by the instruction.
Numerous techniques have been introduced to reduce power consumption within a processing architecture that uses one or more CPUs. For example, in some systems, when a predetermined amount of idleness is identified, functionality is provided that enables the CPU to transition into one of several available reduced power states. Transitioning the CPU into reduced power state may include, reducing the voltage and/or clock speed of the CPU, disabling CPU subsystems, and the like. Each successively deeper reduced power state provides greater levels of power savings but is also associated with a greater latency. Stated differently, the deeper the reduced power state a CPU enters, the greater the time period (“latency”) before the CPU is able to return to a working state.
There is an increasing performance gap between CPUs and I/O systems that has resulted in larger numbers of idle CPU cycles between fetch operations. For example, processor speeds have traditionally doubled every 18-24 months without a matching increase in the performance for I/O devices. As a result, when a CPU requests a memory fetch for data stored on an I/O device, the CPU will usually have idle CPU cycles until request can be satisfied. While existing systems quantify the idleness of a computer over a given period of time to determine whether a CPU should transition into a reduced power state, additional power savings may be achieved with a granular power reduction scheme in which a CPU is able to transition into a reduced power state while waiting for an operation to be satisfied.